Why needs ESD protection for mobile?
- The human body will accumulate static electricity because of various factors (such as the human being walks with air friction), then if they come into contact with the IC or other electronic products, due to the difference in potential, the IC or other products provide the path of electrostatic dissipation, it will cause the occurrence of the conduction of electrostatic charge, and finally reach the balance state. In a very short time (ns) of this process will produce a very high voltage.
- When humans use electronic products such as Mobile phone, PDA, computers etc., it will cause different statics discharge. The transient static with extremely high voltage will damage the products. Therefore, to add suitable ESD protection (ex. Varistors) is necessary.
ESD Standard: IEC61000-4-2
ESD Array Series
|Mobile Phone||Interface||MLE||ULC||ESD Array||ESD+EMI||EMI||TVS||MLC|
|Buttons||Keypad, Push Butto||V||V||V||V||V|
How to Select Model
What are criteria need to comply with?
- Is the power voltage of circuit less than or equal to working voltage of varistors?
- Will the leakage current have heat effect or other effects, at normal working voltage situation?
- To calculate the maximum transmission speed in circuit and decide the suitable capacitance.
ESD protection design starts from PCB:
- The ESD direct current cause the pin of components permanent damage: This ESD surge current occurs by external parts (such as a keyboard, or I/O connectors). To prevent this direct damage, using a series resistor or capacitors in parallel can limit ESD current through IC.
- ESD current flowing through the circuit resulting in reset or damaged: most of the designers assume that ground circuit is low impedance, after ESD pulse, the impedance of the IC ground is very prone to ground bounce, this ground bounce will make IC reset or locked, such as locked, the IC is very easy to be destroyed by power.
- Indirect coupling of the electromagnetic field: such as the discharge of the vertical plate and horizontal plate, it makes the circuit reset. For the report of high-impedance components damaged, this failure mode is depends on PCB loop circuit area and whether construction shielding is good or not. For the protection of ESD, it can proceed from the construction shielding and PCB layout design.
ESD protection used on the PCB design technology:
- The PCB layout arranged and discharge gap, which is acute triangle, copper foil tip, interval 6-10 mil approximately and one end connect to the earth.
- PCB layout must be considered to reduce the sensitivity of the electromagnetic field coupling. Using lots of anti-coupling capacitors can reduce the circuit area. Anti-coupling capacitors should be selected high voltage ceramic capacitors and these capacitors must be put close to the I/O connectors. High voltage ceramic capacitors put on the VCC and ground near PCB connector, which not only reduces the loop area, also with function of decoupling. Besides, the high resonant frequency by-pass capacitors between power and ground can reduce the reaction of indirect coupling of the induction field strength and electromagnetic fields, but the capacitor equivalent series inductance (ESL) and equivalent series resistors as low as possible.
- The PCB layout can use low-pass filter to release the ESD energy. The low-pass filter is combination of capacitors and inductors, which can prevent the high frequency ESD energy into the system. The inductors will present high impedance for surge, and thus reduce the energy intruded into system. The capacitor is put at the input of inductor will lead the ESD high frequency spectrum bypass to the ground.
- On PCB, it can utilize the clamping circuit to suppress the transient high voltage, such as transient voltage suppressor diodes. It must choose the specification of diodes which can withstand a few kV voltage and quick response dv / dt pulse and consume high-current
- In PCB layout design, the component which is sensitive in ESD can be isolated with other area by trenches method, in order to prevent the transfer of the ESD or coupling to other parts.
- For the electromagnetic coupling of indirect discharge and the arcing effect, adopting the multilayer board can enhance the protection for more than 10 times, compared to a single-layer board.
In actual test, many manufacturers release the clamping voltage determined by a rise time 8μs and a rise continuing 20μs pulse. Most of the clamping voltage information shown in product datasheet is applied to the device at 1A pulse and sometimes will apply to a higher pulse current. This pulse can obtain repeatedly and easy to measure and thus it is widely used. Unfortunately, this pulse does not mean ESD pulse. The ESD pulse only has 1ns rise time, duration 60ns. In addition, the IEC 61000-4-2 level 4, the clamping voltage is very different between peak current 30A and 1A pulse.
To adopt standard 1A pulse, the clamping voltage of most semiconductor ESD protection diodes usually mark 8 ~ 15V. But, the clamping voltage will reach 50 ~ 100V at 8kV IEC 61000-4-2 test. This is determined by other characteristics of diodes, such as the dynamic resistance.
Some ESD manufacturers also provide ESD pulse waveform, but it is easy to be misunderstood. For example, manufacturers often use the attenuator to protect the test equipment from damage. However, the waveforms in the datasheet will not show the impact of attenuator. There will be 5 to 10 times tolerance existed for clamping voltage.